Spin torque transfer magnetic random access memory (STT-MRAM) is a memory technology featuring non-volatility, fast read/write access, high endurance and zero standby power. Each STT-MRAM cell has a magnetic tunneling junction (MTJ) as the storage element and an n-channel metal oxide semiconductor (nMOS) transistor as the access control device. The MTJ includes two ferromagnetic layers, namely, the reference layer and the free layer, separated by a tunneling oxide layer. The magnetization of the reference layer is fixed, while that of the free layer may be changed by passing a driving current polarized by the reference layer. The MTJ resistance is determined by the relative magnetization directions between the reference layer and free layer. That is, the MTJ is in a high resistance state and a low resistance state, respectively, when the magnetization directions are anti-parallel and parallel, respectively. Compared with conventional magnetic random access memory (MRAM), for example, the STT-MRAM has higher scalability with much less write current required. Therefore, STT-MRAM has been considered to be a promising candidate for the next generation non-volatile memories (NVM).
In STT-MRAM, the reliability of data is affected by the process variability induced statistical parametric variations, i.e., variations in the tunneling oxide thickness (t) and cross-section area (A). These variations may affect both the static and dynamic behaviors of the MTJ, resulting in cell failures. Cell failures may be reduced by improving the device design, the material used, and the wafer processing for STT-MRAM. Such improvements may be restricted by physical parameters and conditions.
Another approach is to provide a coding scheme for STT-MRAM. An exemplary (typical) system architecture 100 of a STT-MRAM channel 102 with a slicer 104 (i.e., a threshold detector) and conventional Error Correction Codes (ECCs) such as the Hamming code or Bose-Chaudhuri-Hoquenghem (BCH) code with hard-decision decoding is shown in FIG. 1.
In the system architecture 100, input user data 106 is first encoded by a Hamming/BCH encoder 108 and then transferred to the STT-MRAM channel 102. Hard decoding is subsequently performed by a Hamming/BCH decoder 110 to obtain the recovered data 112.
The conventional threshold detector is a hard output detector. In one example for binary signaling, received pulses are sampled and the resulting voltages are compared with a single threshold. If a voltage is greater than the threshold, it is considered to be definitely a “1” regardless of how close it is to the threshold. If the voltage is less than the threshold, it is considered to be definitely a “0”. Hard-decision decoding, or interchangeably referred to as hard decoding, takes a stream of detected bits of “0”s or “1”s output from the threshold detector, and can correct a few errors based on the detected bits of “0”s or “1”s depending on the error correction capability of the code. That is, in decoding performed through hard decisions, bits are treated as either correct or flipped in polarity. The codes used may be conventional ECCs, such as Hamming codes or BCH codes, which are capable of correcting a limited number of errors.
There is therefore a need to provide more efficient coding and detection schemes to correct more STT-MRAM cell failures due to, for example, process variability induced parametric variations such as variations in tunneling oxide thickness and variations in tunneling oxide cross-section, the switching current threshold distribution which causes write failure and/or read failure of the cell, and parasitic effects such as parasitic capacitance of the cell.